TI DP83848I is a robust fully featured 10/100 single port Physical Layer device offering low power consumption, including several intelligent power down states. These low power modes increase overall product reliability due to decreased power dissipation. Supporting multiple intelligent power modes allows the application to use the absolute minimum amount of power needed for operation. In addition to low power, the DP83848I is optimized for cable length performance far exceeding IEEE specifications.
The DP83848I includes a 25MHz clock out. This means that the application can be designed with a minimum of external parts, which in turn results in the lowest possible total cost of the solution.
The DP83848I easily interfaces to twisted pair media via an external transformer and fully supports JTAG IEEE specification 1149.1 for ease of manufacturing. Additionally both MII and RMII are supported ensuring ease and flexibility of design.
Low-Power 3.3-V, 0.18-µm CMOS Technology
Low-Power Consumption < 270 mW Typical
3.3-V MAC Interface
Auto-MDIX for 10/100 Mb/s
Energy Detection Mode
25-MHz Clock Output
SNI Interface (Configurable)
RMII Rev. 1.2 Interface (Configurable)
MII Serial Management Interface (MDC and MDIO)
IEEE 802.3 MII
IEEE 802.3 Auto-Negotiation and Parallel Detection
IEEE 802.3 ENDEC, 10BASE-T Transceivers and Filters
IEEE 802.3 PCS, 100BASE-TX Transceivers and Filters
IEEE 1149.1 JTAG
Error-Free Operation up to 150 Meters
Single Register Access for Complete PHY Status
10/100 Mb/s Packet BIST (Built in Self Test)
LQFP-48 Package (7mm) × (7mm)
Programmable LED Support for Link, 10/100 Mb/s Mode, Activity, Duplex and Collision Detect
Integrated ANSI X3.263 Compliant TP-PMD Physical Sub-Layer with Adaptive Equalization and Baseline Wander Compensation
Automotive / Transportation
Industrial Controls and Factory Automation
General Embedded Applications
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